Sequential Circuit Test Generationin

|Test generation using deterministic fault-oriented algorithms is highly complex and time-consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the tness of each candidate test. Various GA parameters are studied, including alphabet size, tness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the IS-CAS89 sequential benchmark circuits, and execution times were signiicantly lower than in a deterministic test generator in most cases. Simulation-based test generation has been used to avoid the long execution times of deterministic algorithms and to reduce the complexity of the test generator. In particular, in a simulation-based approach, processing occurs in the forward direction only; i.e., no backtracing is required. Therefore, complex component types are more easily handled. As a result, the development time is greatly reduced. Seshu and Freeman 1] rst proposed simulation-based test generation, and several simulation-based test generators have since been developed 2, 3, 4, 5, 6, 7]. Breuer 2] used a fault simulator to evaluate sets of random vectors and to select the best vector to apply in each time frame. Weighted random pattern generators were interfaced with fault simulators in 3, 4, 5], and high fault coverages were obtained for combinational circuits. The test generators in 6, 7] were also built around fault simulators, but only candidate vectors of Hamming distance one from the previous vector were considered. Speciic faults were targeted in 6], with a backtrace step used to select the bit to be ipped. Cost functions calculated during concurrent fault simulation were used to evaluate candidate vectors in 7]. While development of these random and mutation-based test generators was simpliied and test generation time was reduced , the test sets generated were typically much longer than those generated by deterministic test generators. Genetic algorithms (GAs) were rst used as a framework for simulation-based test generation in 8, 9], but only combina-tional circuits were handled in 9]. The CRIS test generator 8] used a logic simulator to evaluate candidate test sequences; consequently the test sets generated often had lower fault cov-erages than those generated by a deterministic test generator. Furthermore, a heuristic crossover scheme was …